ELEC 3004 Digital Systems 2

Credit Points 10

Legacy Code 300019

Coordinator Qi Cheng Opens in new window

Description This unit covers modern logic design techniques and the process of creating logic circuits and systems from design specifications to implementation. Topics include logic design techniques for combinational and sequential logic circuits; hardware description language (HDL); logic circuit implementation using an HDL; state-of-the-art logic circuit design tools; and programmable logic devices.

School Eng, Design & Built Env

Student Contribution Band HECS Band 2 10cp

Check your HECS Band contribution amount via the Fees page.

Level Undergraduate Level 3 subject

Pre-requisite(s) ELEC 1001

Learning Outcomes

On successful completion of this subject, students should be able to:
  1. Describe functions of encoders/decoders, adders/subtractors, multiplexers/demultiplexers and their design procedures; and design them using VHDL (combinational logic)
  2. Describe functions of flip-flops, registers, counters, finite-state machines and their design procedures; and design them using VHDL (sequential logic)
  3. Build ALUs using VHDL
  4. Describe VHDL memory functions and use them to design RAM units
  5. Describe VHDL bus and I/O functions and use them to design bidirectional bus and tri-state buses
  6. Implement logic circuits on FPGA boards

Subject Content

Logic function optimization
State diagram, state table
Logic circuit design
Hardware description languages (VHDL)
Statements, structures, data, variable, signal, type
Logic circuit modelling using VHDL
RAM implementation
Bus implementation
ALU implementation
Field programmable gate array devices
Implementation of logic circuits on FPGA

Assessment

The following table summarises the standard assessment tasks for this subject. Please note this is a guide only. Assessment tasks are regularly updated, where there is a difference your Learning Guide takes precedence.

Item Length Percent Threshold Individual/Group Task
2 X Assignments Approximately 10 questions each, individual theoretical and programming tasks 15 N Individual
5 X Lab Activities and Reports (Individual) 3 hours per session/Approximately 5-10 pages 20 N Individual
Final Exam 2 hours 65 N Individual

Teaching Periods

2022 Trimester 1

Sydney City

Day

Subject Contact Peter Lendrum Opens in new window

Attendance Requirements 80% attendance rate is imposed in all core subjects’ due to the nature of class activities that are aligned with subject assessments.

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2022 Trimester 2

Sydney City

Day

Subject Contact Peter Lendrum Opens in new window

Attendance Requirements 80% attendance rate is imposed in all core subjects’ due to the nature of class activities that are aligned with subject assessments.

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2022 Semester 2

Penrith (Kingswood)

Day

Subject Contact Qi Cheng Opens in new window

Attendance Requirements 80% attendance rate is imposed in all core subjects’ due to the nature of class activities that are aligned with subject assessments.

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Parramatta - Victoria Rd

Day

Subject Contact Qi Cheng Opens in new window

Attendance Requirements 80% attendance rate is imposed in all core subjects’ due to the nature of class activities that are aligned with subject assessments.

View timetable Opens in new window